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ISL6412
Data Sheet January 2004 FN9067
Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit
The ISL6412 is an ultra low noise triple output LDO regulator with microprocessor reset circuit and is optimized for powering wireless chip sets. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultraclean 2.8V (LDO3). On chip logic provides sequencing between LDO1 and LDO2 for the BBP/MAC and the I/O supply voltage outputs. LDO3 features ultra low noise that does not typically exceed 30V RMS to aid VCO stability. High integration and the thin Quad Flat No-lead (QFN) package makes the ISL6412 an ideal choice to power many of today's small form factor industry standard wireless cards such as PCMCIA, mini-PCI and Cardbus-32. The ISL6412 uses an internal PMOS transistor as the pass device. The ISL6412 also integrates a reset function, which eliminates the need for the additional reset IC required in WLAN applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after Vin has risen above the reset threshold. FAULT1 indicates the loss of regulation on LDO1.
Features
* Small DC-DC Converter Size - Three LDOs and Reset Circuitry in a Low-Profile 4x4mm QFN Package * High Output Current - LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA - LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA - LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA * Ultra-Low Dropout Voltage - LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA - LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA * Ultra-Low Output Voltage Noise - <30VRMS (typ.) for LDO3 (VCO Supply) * Stable with Smaller Ceramic Output Capacitors * Extensive Protection and Monitoring Features - Over current protection - Short circuit protection - Thermal shutdown - FAULT indicator * Logic-Controlled Shutdown Pin * Integrated Microprocessor Reset Circuit - Programmable Reset Delay
Ordering Information
PART NUMBER ISL6412IR ISL6412IRZ NOTES: 1. "Z" Suffix: These products are packaged in 16 ld QFN packages that are MSL level 1 at 255-260oC peak reflow temperature, which exceeds the IPC J Std-020B requirements for MSL level 1. The lead free and green products employ special lead free material sets including 100% matte tin plate termination finish, which is compatible with either Sn/Pb or lead free soldering operations. 2. Tape and Reel available. Add "-T" suffix for Tape and Reel Packing Option. TEMP. RANGE (oC) -40 to +85 -40 to +85 PACKAGE PKG. DWG. #
* Proven Reference Design for a Total WLAN System Solution * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint Improves PCB Efficiency and Is Thinner in Profile * Lead (Pb) - Free Packaging
16 Ld 4x4 QFN L16.4x4 16 Ld 4x4 QFN L16.4x4
Applications
* PRISM(R) 3 Chipsets - ISL37106P * WLAN Cards - PCMCIA, Cardbus32, MiniPCI Cards - Compact Flash Cards * Liberty Chipset * Hand-Held Instruments
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved. All Rights Reserved. PRISM(R) 3 and PRISM GTTM are trademarks of GlobespanVirata, Inc. All other trademarks mentioned are the property of their respective owners.
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ISL6412 Pinouts
ISL6412 (QFN) TOP VIEW
FAULT1
VIN 14
16 RESET CT SHDN NC 1 2 3 4 5 OUT3
15
13 12 11 10 9 OUT1 CC1 OUT2 CC2
6 CC3
7 GND3
Typical Application Schematic
+3.3V VIN + C8 3.3F 14 VIN 13 VIN 16 15
GND
VIN 8
NC
FAULT1
+1.8V VOUT1
NC
C7 0.01F
1 2 3 4
RESET CT SHDN NC
ISL6412
12 OUT1 11 CC1 10 OUT2 9 CC2 C4 0.033F C3 0.033F C2 3.3F C1 3.3F
+2.8V VOUT2
+2.8V VOUT3 C5 3.3F
2
5 6 7 8 C6 0.033F
OUT3 CC3 GND3 GND
ISL6412 Functional Block Diagram
GM VIN 13
VIN + LDO1 Vin BAND GAP REF. 1.2V 15 FAULT1 WINDOW COMP OUT1
14
12
CC1 GM THERMAL SHUT DOWN 150o C + LDO2 OUT2
11
10
Vin GM
CC2
9
CONTROL LOGIC 3 SHDN
+ LDO3
OUT3
5
ENABLES 2
CT
RESET 1 RESET CC3 6
8
GND
7 GND3
3
ISL6412 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 4 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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